A conventional PN junction diode structure can be used for electrostatic discharge (ESD) protection. However, these prior art PN junction diode structures are designed for low voltage CMOS technology. Standard CMOS technology continues to scale, and cannot withstand high voltages. Power technologies integrate advanced CMOS technology (with application voltages between 1.8V and 5V), with circuitry in the 20 to 120V application range. Today, the continued scaling of CMOS technology provides a larger margin between these high voltage CMOS and low voltage CMOS. In the low voltage CMOS technology, the breakdown voltages of the CMOS junctions are less than 20V. Therefore, there is a need for a semiconductor diode structure (and a method for forming the same) which can withstand higher voltages than those of the prior art.